1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
2. Background Art
Silicon carbide (SiC) semiconductors have several advantages over traditional silicon (Si) semiconductors such as a wider band gap, greater dielectric breakdown field strength, and higher thermal conductivity. Furthermore, silicon carbide semiconductors have sufficiently high bulk mobility (carrier mobility), and like silicon semiconductors, the surface of a silicon carbide semiconductor can be thermally oxidized to create an insulating layer. For these reasons, in recent years silicon carbide has seen increased use as the semiconductor material of choice in the manufacture of power semiconductor devices, where silicon carbide semiconductors can provide performance that exceeds the limits of traditional silicon semiconductors.
Among the various types of power semiconductor devices, insulated-gate type semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs) have seen a particularly large amount of research and development in recent years. For example, MOSFET devices have become one of the most commonly used types of devices in the 10 kV and lower withstand voltage class, and IGBT devices have recently become more prominent in withstand voltage classes beyond 10 kV.
Bidirectional devices that have bidirectional withstand voltage properties have become indispensable in applications in which the flow of power must be controlled in both directions. Common applications of bidirectional devices include protection circuits in lithium-ion batteries, multilevel power converters, and failure isolation elements that are used in power transmission systems to isolate points of failure from the rest of the system. Bidirectional MOSFET devices typically have circuit configurations such as those shown in FIGS. 23 and 24. FIGS. 23 and 24 are circuit diagrams illustrating common circuit configurations of bidirectional devices. As shown in FIGS. 23 and 24, the MOSFET devices 101a and 101b are three-terminal devices that include source terminals 102a and 102b, drain terminals 103a and 103b, and gate terminals 104a and 104b, respectively.
In a bidirectional device, the drain terminals 103a and 103b or the source terminals 102a and 102b of two semiconductor devices such as the MOSFET devices 101a and 101b are electrically connected (see Patent Documents 1 and 2, for example). FIG. 23 depicts a bidirectional device 111 in which two MOSFET devices 101a and 101b share a common drain terminal 103. FIG. 24 depicts a bidirectional device in which two MOSFET devices 101a and 101b share a common source terminal 102. The reference characters 104a and 104b indicate gate terminals. The reference characters 105a and 105b indicate built-in body diodes in the MOSFET devices 101a and 101b. 
Next, an example of a multilevel power converter will be described as a usage example of the bidirectional device 111 shown in FIG. 23. FIG. 25 is a circuit diagram illustrating the circuit configuration of a multilevel power converter. The circuit configuration shown in FIG. 25 is one phase of a three-level inverter. As shown in FIG. 25, the bidirectional device 111 is connected to a midpoint potential point (an output terminal Out) between two main switch IGBT devices 112 and 113 and to a neutral point N created by dividing a bus voltage Vbus between two DC-link capacitors 110. The bidirectional device 111 serves as a neutral point clamp that clamps the midpoint potential between the two IGBT devices 112 and 113. AC power is supplied to an inductive load 114 from the midpoint potential point between the two IGBT devices 112 and 113.
In the bidirectional device 111, the MOSFET devices 101a and 101b are typically formed on two separate semiconductor substrates (semiconductor chips) which are then mounted on an insulating substrate. FIG. 26 is a plan view illustrating an example configuration inside a conventional semiconductor package case. As shown in FIG. 26, the MOSFET devices 101a and 101b are formed on separate semiconductor chips. The rear surface electrodes (drain electrodes) of the MOSFET devices 101a and 101b are each connected to a copper (Cu) wiring layer formed on the surface of a ceramic substrate 125 (an insulating substrate) such as a direct bonded copper (DBC) substrate. This copper wiring layer is connected to a drain pad 123 via a wire and serves as a common drain terminal 103 for the MOSFET devices 101a and 101b. 
The front surface electrodes (source terminals 102a and 102b) of the MOSFET devices 101a and 101b are connected via wires to source pads 122a and 122b, respectively, mounted on the surface of the insulating substrate 125. Moreover, the front surface electrodes of the MOSFET devices 101a and 101b are connected via wires to auxiliary source terminals 126a and 126b, respectively, mounted on the surface of the insulating substrate 125, for example. The auxiliary source terminals 126a and 126b serve as source potential connection terminals when a gate signal is applied. The gate electrodes (gate terminals 104a and 104b) of the MOSFET devices 101a and 101b are connected via wires to gate pads 124a and 124b, respectively, mounted on the surface of the insulating substrate 125.
Moreover, forming both MOSFET devices 101a and 101b monolithically on the same semiconductor chip is also a well-known technique. Patent Document 1 discloses a semiconductor device package in which two MOSFET devices that together form a bidirectional switch are formed on a single semiconductor chip which is then mounted on an insulating substrate and housed within a case. FIG. 27 is a plan view illustrating a configuration of a conventional semiconductor package from the top side (that is, the side on which the case lid is arranged). FIG. 28 is a cross-sectional view of a cross section taken along line AA-AA′ in FIG. 27. FIGS. 27 and 28 correspond to FIGS. 6A and 6B in Patent Document 1, respectively.
As shown in FIGS. 27 and 28, the MOSFET devices 101a and 101b are both formed on a single semiconductor chip 131 (a silicon substrate) which is then housed in a case 130. The source terminals of the MOSFET devices 101a and 101b (not shown in the figures) are connected, respectively, to external connection terminals 132a and 132b that are drawn out to the exterior of the case 130 and left exposed. The semiconductor chip 131 in which the MOSFET devices 101a and 101b are formed provides a common drain resistance 133. A rear surface electrode 134 is formed on the rear surface of the silicon substrate 131 in order to reduce this drain resistance 133.
Moreover, it can be assumed that the MOSFET devices used to form the bidirectional switch in Patent Document 1 have a low withstand voltage because the bidirectional switch is mounted in a dual flat no-lead (DFN) package. Moreover, the structure used between the MOSFET devices 101a and 101b that are formed on the same substrate is not described in detail in Patent Document 1. If the MOSFET devices 101a and 101b had a high withstand voltage, an edge termination structure would be required to maintain a withstand voltage between the two MOSFET devices 101a and 101b. In silicon carbide semiconductor devices, for example, a junction termination extension (JTE) structure is typically used for the edge termination structure.
Next, a JTE structure will be described. FIG. 29 is a cross-sectional view of an example edge termination structure in a conventional semiconductor device. As shown in FIG. 29, an n− drift layer 142 is formed on the front surface of an n+ semiconductor substrate 141 (a semiconductor chip) that serves as an n+ drain layer. A p+ well region 143 that is part of the semiconductor structure is formed within the active region in the surface layer of the front surface of the n− drift layer 142 (that is, the surface opposite to the n+ semiconductor substrate 141 side). The p+ well region 143 and the n− drift layer 142 form the primary junction of the device. In the off state, the depletion layer 152 expands outwards from the p-n junction between the p+ well region 143 and the n− drift layer 142. Here, the term active region refers to the region through which current flows when the device is in the on state.
Moreover, a p-type JTE region 144 is formed in the surface layer on the front surface of the n− drift layer 142 (that is, the surface opposite to the n+ semiconductor substrate 141 side). The JTE region 144 contacts the chip edge side of the p+ well region 143 and surrounds the periphery of the active region. The p-type JTE region 144 has a lower concentration of impurities than the p+ well region 143, and the JTE structure is formed by arranging the p-type JTE region 144 at the termination of the p-n junction between the p+ well region 143 and the n− drift layer 142. Moreover, an n+ channel-stop region 145 is formed in the surface layer on the front surface of the n− drift layer 142 (that is, the surface opposite to the n+ semiconductor substrate 141 side). The channel-stop region 145 is separated from the p-type JTE region 144 and positioned nearer to the chip edge than the JTE region 144. The edge termination structure includes everything from the boundary between the p+ well region 143 and the p-type JTE region 144 to the edge of the chip.
An interlayer insulating film 146 is formed on the surfaces of the p+ well region 143, the p-type JTE region 144, and the n+ channel-stop region 145 from the edge termination structure side edge of the p+ well region 143 to the edge of the chip. A source electrode 147 is arranged in contact with the p+ well region 143. A passivation film 151 is formed on the surfaces of the source electrode 147 and the interlayer insulating film 146 from the edge termination structure side edge of the source electrode 147 to the edge of the chip. A drain electrode 148 is formed on the rear surface of the n+ semiconductor substrate 141. A scribe region 149 is formed on both edges of the chip. A rough surface 150b is formed within the scribe region 149 on each edge face 150a of the chip when the overall semiconductor wafer is diced into individual chips.
FIG. 30 illustrates another example of an edge termination structure. FIG. 30 is a cross-sectional view of another example of an edge termination structure in a conventional semiconductor device. As shown in FIG. 30, when forming the MOSFET devices 101a and 101b on the same semiconductor substrate, an n+ channel-stop region 145 may be arranged in the center, with the MOSFET devices 101a and 101b arranged symmetrically on either side thereof. This makes it possible to reduce the overall chip size because there is no need to provide a scribe region 149 between the adjacent edges of the two semiconductor chips for the MOSFET devices 101a and 101b to facilitate later mounting those two chips separately on the insulating substrate 125 (see FIGS. 26 and 29).
Therefore, when mounting the single monolithic semiconductor chip that contains the MOSFET devices 101a and 101b on an insulating substrate, the area of the copper wiring layer on the insulating substrate 125 that serves as the common drain terminal 103 for the MOSFET devices 101a and 101b can be made smaller than when mounting two separate semiconductor chips for the MOSFET devices 101a and 101b on the insulating substrate 125. In FIG. 30, the letters a and b are appended to each p+ well region 143, each p-type JTE region 144, each source electrode 147, and each depletion layer 152 that extends from the primary device junction in order to indicate to which MOSFET device (101a or 101b) each portion belongs.
Moreover, Patent Document 3 discloses a MOSFET edge termination structure in which a plurality of trenches are formed on either side of the primary junction of the MOSFET device and p+ layers or Schottky contacts are formed at the bottom of each trench. Next, the edge termination structure disclosed in Patent Document 3 will be described. FIG. 31 is a cross-sectional view of another example of an edge termination structure in a conventional semiconductor device. FIG. 31 corresponds to FIG. 2 in Patent Document 3. As shown in FIG. 31, an n− drift layer 142 is formed on the front surface of an n+ semiconductor substrate 141 that serves as an n+ drain layer.
A p-type well region 153 is formed in the active region in the surface layer of the front surface of the n− drift layer 142 (that is, the surface opposite to the n+ semiconductor substrate 141 side). A trench (an active region trench) 154 is formed. The active region trench 154 goes through the entire p-type well region 153 in the substrate thickness direction and extends into the n− drift layer 142. The active region trench 154 divides the p-type well region 153 into a plurality of regions. Within the active region trench 154, a gate insulation film 155 and a gate electrode 156 are formed. N+ source regions 157 are provided selectively in the p-type well region 153 and are arranged in contact with the gate insulation film 155 formed on the sidewalls of the active region trench 154.
Moreover, a p-type termination region 163 is formed in the edge termination structure region in the surface layer of the front surface of the n− drift layer 142 (that is, the surface opposite to the n+ semiconductor substrate 141 side). Trenches (termination region trenches) 164 are formed. The termination region trenches 164 go through the entire p-type termination region 163 in the substrate thickness direction and extend into the n− drift layer 142. The termination region trenches 164 divide the p-type termination region 163 into a plurality of p-type regions. The portions of the p-type termination region 163 between the termination region trenches 164 function as p-type JTE regions 162.
P+ regions 161 are formed on the exposed surfaces of the n− drift layer 142 at the bottoms of the termination region trenches 164. An insulating film 165 is formed along the inner walls of the termination region trenches 164. The interior regions of the termination region trenches 164 are not completely filled by the insulating film 165. An interlayer insulating film 158 is formed covering the gate electrode 156, the p-type JTE regions 162, and the p-type termination region 163. A source electrode 159 is arranged in contact with the n+ source regions 157 and the p-type well region 153 via contact holes that go through the interlayer insulating film 158 in the thickness direction thereof. The source electrode 159 is electrically insulated from the gate electrodes 156 by the interlayer insulating film 158. A drain electrode 160 is formed on the rear surface of the n+ semiconductor substrate 141.
In the semiconductor devices shown in FIGS. 30 and 31, the withstand voltage of the front surface of the device is divided between the p-type JTE regions 144 and the portions of the n− drift layer 142 between the p-type JTE regions 144 and the n+ channel-stop region 145.
Moreover, other types of edge termination structures for MOSFET devices such as the following edge termination structure have also been proposed. FIG. 32 is a cross-sectional view of another example of an edge termination structure in a conventional semiconductor device. There are of five primary differences between the semiconductor device shown in FIG. 32 and the semiconductor device shown in FIG. 31. First, a p-type well region 153 is formed over the entire front surface of the n− drift layer 142 (that is, the surface opposite to the n+ semiconductor substrate 141 side). Here, the p-type well region 153 also serves as a p-type termination region and as a p-type JTE region. Second, termination region trenches 164 that are formed as part of the edge termination structure are completely filled by an insulating film 166. Third, a p+ region 161 is only formed at the bottom of the termination region trench 164 that is closest to the active region.
Fourth, p+ contact regions 167 are formed over the entire front surface of the p-type well region 153 (that is, the source electrode 159-side surface) from the active region to the chip edge side of the edge termination structure. Fifth, shield electrodes 168 that cover the portions of the p-type well region 153 between the termination region trenches 164 are formed. The shield electrodes 168 contact the respective p+ contact regions 167 via contact holes that go through an interlayer insulating film 158 and a gate insulation film 155 down to the p+ contact regions 167. The source electrode 159 contacts the p+ contact region 167 in the active region (see Patent Document 4). FIG. 32 corresponds to FIG. 2 in Patent Document 4.
Non-Patent Document 1 discloses another example of a MOSFET edge termination structure. The semiconductor device disclosed in Non-Patent Document 1 has a super junction structure in which the drift layer includes n-type regions and p-type regions that have a high concentration of impurities and that are alternately arranged parallel to the main substrate surface to form a parallel p-n layer. This type of semiconductor device is known as a super junction semiconductor device. Next, the edge termination structure of the super junction semiconductor device disclosed in Non-Patent Document 1 will be described. FIG. 33 is a cross-sectional view of another example of an edge termination structure in a conventional super junction semiconductor device. FIG. 33 corresponds to FIG. 3 in Non-Patent Document 1. As shown in FIG. 33, an n− drift layer 172 is formed on the front surface of an n+ semiconductor substrate 171 that serves as an n+ drain layer.
P-type well regions 173 are formed in the active region in the surface layer of the front surface of the n− drift layer 172 (that is, the surface opposite to the n+ semiconductor substrate 171 side). An active region trench 174a is formed in the active region. The active region trench 174a goes through the entire p-type well region 173 in the thickness direction thereof and extends into the n− drift layer 172. Moreover, a termination region trench 174b is formed in the boundary region between the active region and the edge termination structure. The termination region trench 174b goes through the entire p-type well region 173 in the thickness direction thereof and extends into the n− drift layer 172. The active region trench 174a and the termination region trench 174b go through more than half of the thickness of the n− drift layer 172 and reach down to near the interface between the n+ semiconductor substrate 171 and the n− drift layer 172.
P-type regions 175 are formed on the exposed surfaces of the n− drift layer 172 on the interior walls of the active region trench 174a and the termination region trench 174b. The n− drift layer 172 and the p-type regions 175 form a charge balance structure. The interior regions of the active region trench 174a and the termination region trench 174b are filled by an insulating film 176. N+ source regions 177 are provided selectively in the p-type well regions 173. On the front surfaces of the portions of the p-type well regions 173 between the n− drift layer 172 and the n+ source regions 177, a gate insulation film 178 and a gate electrode 179 are formed.
An interlayer insulating film 180 is formed covering the gate electrode 179. A source electrode 181 is arranged in contact with the n+ source regions 177 and the p-type well region 173 via contact holes that go through the interlayer insulating film 180 in the thickness direction thereof. The source electrode 181 is electrically insulated from the gate electrode 179 by the interlayer insulating film 180. Moreover, the source electrode 181 extends over a portion of an interlayer insulating film 180 that covers the termination region trench 174b. The source electrode 181 thereby covers a portion of the termination region trench 174b, with the interlayer insulating film 180 disposed therebetween. A drain electrode 182 is formed on the rear surface of the n+ semiconductor substrate 171.
Patent Document 5 discloses another example of a MOSFET edge termination structure. Patent Document 5 discloses a structure in which a semiconductor layer having a first conductivity type includes a device portion and a device termination portion. A trench structure is formed in the surface of the device termination portion, and the trench is filled with an insulating material.
Patent Document 6 discloses another example of a MOSFET edge termination structure. In Patent Document 6, a trench is formed in an n-type semiconductor substrate and filled with an insulating film. A recess deeper than the thickness of a p-type well region is formed in this insulating film, and a field plate electrode is formed within the recess.
Patent Document 7 discloses a semiconductor device in which vertical silicon carbide MOSFET devices are arranged on the same semiconductor substrate. The semiconductor device disclosed in Patent Document 7 includes: a silicon carbide substrate having a front surface and a rear surface; an isolation region formed all the way from the front surface to the rear surface of the substrate; and first and second vertical MOSFET devices arranged on either side of the isolation region.